The present invention relates to a semiconductor apparatus, and more particularly, it relates to a technology effectively used for a semiconductor apparatus equipped with a highly reliable semiconductor memory circuit of a large storage capacity.
With regard to a semiconductor memory, there are mainly a random access memory (RAM), and a read only memory (ROM). Among others, a dynamic RAM (DRAM) is most often used as a main memory of a computer. A memory cell for storage includes one capacitor, and a transistor for storing a charge therein, and reading the charge therefrom. This memory is suitable for a large-scale system, because it is realized as a RAM by a minimum number of components. Thus, such memories have been mass-produced at relatively low costs.
In the conventional DRAM, an information charge stored in the capacitor is lost by a pn junction (leakage) current present in the memory cell. Accordingly, before the loss, the memory cell is cyclically refreshed (reproducing and writing operations) to hold stored information. This cycle is called a refreshing period, which is currently around 100 ms. This period must be made longer as a storage capacity is increased more. That is, the leakage current must be suppressed, which has become increasingly difficult with device microfabrication. As a technology for omitting the refreshing operation, the inventors presented a PLED memory in U.S. patent application Ser. No. 09/806,582 filed on Apr. 2, 2001.
A PLED transistor has a vertical structure, where gate electrodes are disposed in both sides of laminated polysilicon layers, e.g., five layers, via an oxide film, and the gate electrodes made of polysilicon in both sides are integrally formed to have always equal potentials. A transistor substrate (channel) is constructed by setting a polysilicon layer provided between a drain and a source of the transistor as an intrinsic polysilicon (intrinsic Poly Si) layer doped with very low concentration of phosphorus and, between such intrinsic poly Si layers, a tunnel film made of, e.g., a thin silicon nitride film, is formed. The tunnel film serves as a stopper for preventing high-concentration phosphorus of a drain or source region from being dispersed to an inner low-concentration layer during transistor formation. To supply a current between the drain and the source, the tunnel film must be formed in a manner that a thickness of each film thereof is not so large. In a center part, the tunnel film is formed to limit an OFF current of the transistor small. That is, the tunnel film serves as a stopper for preventing a hole or an electron generated by poly Si in the transistor of an OFF state from flowing as a current between the drain and the source, and thus a leakage current can be reduced to zero in theory.
However, with regard to a currently available manufacturing technology, it has been discovered that if the foregoing PLED transistor is formed, intrinsic poly Si between the drain and the source, or a defect generated in the tunnel film, cannot be ignored unlike the case in theory. Therefore, to obtain a memory circuit making good use of a characteristic of the PLED transistor, where a leakage current is reduced to zero as in the foregoing, the manufacturing technology of the PLED transistor remains to be improved much more.
An object of the present invention is to provide a semiconductor apparatus equipped with a simply constituted, highly reliable, and large storage-capacity semiconductor memory circuit. Another object of the present invention is to provide an easily operated semiconductor apparatus while achieving high reliability and a large storage capacity. The above, other objects and features of the present invention will become apparent upon reading of the detailed description of the embodiments and the accompanying drawings.
In accordance with an aspect of the present invention, there is provided a semiconductor apparatus, comprising on one semiconductor substrate: a plurality of memory cells, each including a capacitor having first and second electrodes, and a switching device having a control terminal connected to a corresponding word line among a plurality of word lines, and a current channel connected between the first electrode and a corresponding bit line among a plurality of bit lines. In this case, when the semiconductor apparatus is on a first mode, an OFF potential of the word lines is set to be a first potential, when the semiconductor apparatus is on a second mode, an OFF potential of the word lines is set to be a second potential, and the current channel of the switching device is set in a direction vertical the semiconductor substrate.
In accordance with another aspect of the present invention, there is provided a semiconductor apparatus, comprising on one semiconductor substrate: a plurality of memory cells, each including a MOSFET having an information voltage of a capacitor supplied to a gate, and a writing transistor for supplying the information voltage to the capacitor; a plurality of word lines connected to a second electrode of the capacitor, and a gate of the writing transistor; and a plurality of bit lines disposed in a direction orthogonal to the word lines for receiving a writing voltage and a source output of the MOSFET. In this case, when the semiconductor apparatus is on a first mode, an OFF potential of the word lines is set to be a first potential, when the semiconductor apparatus is on a second mode, an OFF potential of the word lines is set to be a second potential, when the semiconductor apparatus is on the first and second modes, an ON voltage of the word lines is set to be a third voltage for turning OFF the writing transistor when a signal corresponding to the information voltage is read to the bit lines, and turning ON the MOSFET when the information voltage of the capacitor is at a high level, and to be a fourth voltage for turning ON the writing transistor when a writing voltage is supplied from the bit lines to the capacitor, and the writing transistor and the semiconductor substrate are insulated from each other by an insulating material.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.